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| ? semiconductor msm7664 1/76 pedl7664-01 ? semiconductor msm7664 ntsc/pal digital video decoder general description the msm7664 is an lsi device that decodes ntsc or pal analog video signals into ycbcr and rgb digital data based on itu-rbt.601. the device has built-in two channels of a/d converters and can accept composite video and s video signals for the input video signals. composite video signals are converted to ycbcr and rgb digital data via the 2-dimensional y/c separation circuit with an adaptive filter. analog video signals can be sampled by a clock at the pixel frequency or at twice the pixel frequency. a decimation filter is built-in for sampling at twice the pixel frequency. input signals are synchronized internally and high-speed locking for color burst is possible. because a fifo buffer is built into the output format circuit, jitter-free output can be obtained even for non-standard signals. the msm7664 is an improved version of the msm7662, and is particularly superior in the picture quality and stabilization of synchronization in the pal decoder as well as the stabilization of synchronization in the decoder under weak electric fields. further, although a part of the registers have been added, the electrical characteristics of both products are almost identical and their pin compatibility makes it possible to use the msm7664 instead of the msm7662. application examples since the synchronization of input signals and high-speed locking for color burst are possible, the device is optimized for applications used by switching multiple cameras. it is also used for various image processing applications because of jitter-free output data through a built-in fifo buffer. even in the pal mode, a yc separation characteristics equivalent to the ntsc mode has been achieved thereby making this lsi ideally suitable for pal mode applications. 8-bit (ycbcr), 16-bit (8-bit (y) + 8-bit (cbcr)), and 24-bit (rgb) output interfaces can be selected as an output mode so that various devices such as monitoring system, digital video memory, digital tv, video processing unit and video communication unit can be selected on the receiving side. pedl7664-01 this version: nov. 1999 preliminary
? semiconductor msm7664 2/76 pedl7664-01 features (? new feature not found on msm7662) input analog signal ntsc/pal composite video signal or s-video signal maximum 5 composite or 2 s-video + 2 composite analog inputs can be connected (switchable by external pins or internal registers) built-in clamp circuits and video amps built-in 8-bit a/d converters (2 channels) 4 selectable output interfaces itu-rbt.656 (conditional) 8-bit (ycbcr) : 8-bit (ycbcr) ycbcr = 4 : 2 : 2/ycbcr = 4 : 1 : 1 (limit) 16-bit (ycbcr) : 8-bit (y) + 8-bit (cbcr) ycbcr = 4 : 2 : 2/ycbcr = 4 : 1 : 1 (limit) 24-bit rgb : 8-bit (r) + 8-bit (g) + 8-bit (b) ? high speed of burst locking has been realized. ? 2-dimensional y/c separation using adaptive comb filter (this filter is bypassed for s-video signal input) ntsc format: 3 lines or 2 lines, pal format: 2 lines (adaptive transition method) ? built-in vertical chrominance filter (straight output without using the filter is possible) selectable data i/o signal synchronization 4 synchronization modes: internal fifo modes (fifo-1, fifo-2) and external field memory modes (fm-1, fm-2) are selectable (fifo-1 is normally selected). compatible pixel frequencies (normal/twice the pixel frequency) 13.5 mhz (13.5/27 mhz) : ntsc/pal itu-rbt.601 12.272727 mhz (12.272727/24.545454 mhz) : ntsc square pixel 14.31818 mhz (14.31818/28.63636 mhz) : ntsc 4fsc 14.75 mhz (14.75/29.5 mhz) : pal square pixel ? recognition of data in the vbi period (closed caption, cgms, wss, macrovision agc and pseudo pulse) and function of reading from i 2 c-bus (only for itu-rbt.601 mode). built-in agc/acc circuits, compatible with a wide range of input levels input level range: C8 db to +3.5 db (0.4 v to 1.5 v) switchable between agc/mgc (fixed gain) and acc/mcc (fixed gain) decimation filter built into input stage, allows easy configuration of filter prior to a/d converter (when input at twice the pixel frequency) automatic ntsc/pal recognition (only for itu-rbt.601) sleep mode ? hi-z mode for output pins multiplex signal recognition (closed caption) during vertical blanking interval, data is output as 8-bit data. i 2 c-bus interface 3.3 v single power supply (i/o 5 v tolerance) package: 100-pin plastic tqfp (tqfp100-p-1414-0.50-k) (product name: msM7664TB) ? semiconductor msm7664 3/76 pedl7664-01 block diagram scan test control logic sleep test[2:0] status2 status3 odd/even status1 hvalid vvalid hsync_l vsync_l synchronization block luminance block digital (agc or mgc + lpf) clksel gains[2:0] ins[2:0] pllsel clkxo clkx2 clkx2o vrcl1 vrt1 vin2 vin3 vin4 clpout2 vrb2 vin6 vin5 ampout2 adin2 vrt2 adin1 ampout1 clpout1 vrb1 vin1 m[7:4] m[2:1] y[7:0] (g[7:0]) epilogue block output formatter 8 bits (r) 8 bits (g) 8 bits (b) 8 bits (y) 8 bits (cbcr) itu-656 & 8 bits (ycbcr) c[7:0] (r[7:0]) b[7:0] prologue block c adc decimation filter line memory (1 kb) 2 (2 dim. y/c separate) chrominance block (acc or mcc + lpf) sda i 2 c-bus control logic scl mode[3:0] reset_l y adc decimation filter analog agc& amp analog agc& amp sw matrix fifo (640w) 24b u, v-vertical filter line memory (1 kb) 2 vbid block ? semiconductor msm7664 4/76 pedl7664-01 pin configuration (top view) 100 99 98 97 96 95 94 93 92 91 90 dagnd ins[0] ins[1] ins[2] gains[0] gains[1] gains[2] dv dd m[0] m[1] dgnd 75 74 73 72 71 70 69 68 67 66 65 hsync_l vsync_l vvalid hvalid odd/even c[0] c[1] c[2] c[3] c[4] c[5] 1 2 3 4 5 6 7 8 9 10 11 dav dd vrt2 vin6 vin5 ad dd agnd adin2 ampout2 clpout2 vrb2 agnd 89 m[2] 88 m[3] 87 m[4] 86 m[5] 85 m[6] 12 agnd 13 vrb1 14 clpout1 15 ampout1 16 adin1 64 c[6] 63 c[7] 62 dgnd 61 dv dd 60 y[0] 84 m[7] 83 status1 82 status2 81 status3 26 27 28 29 30 31 32 33 34 35 36 dagnd mode[0] mode[1] mode[2] mode[3] scan test[2] test[1] test[0] sleep reset_l 37 dv dd 38 dgnd 39 scl 40 sda 41 pllsel 42 clksel 43 b[7] 44 b[6] 45 b[5] 17 vrcl1 18 agnd 19 av dd 20 vin4 59 y[1] 58 y[2] 57 y[3] 56 y[4] 80 clkx2 79 dv dd 78 dgnd 77 clkx2o 76 clkxo 46 b[4] 47 b[3] 48 b[2] 49 b[1] 50 b[0] 21 vin3 55 y[5] 22 vin2 23 vin1 24 vrt1 25 dav dd 54 y[6] 53 y[7] 52 dv dd 51 dgnd 100-pin plastic tqfp ? semiconductor msm7664 5/76 pedl7664-01 pin descriptions pin symbol type description 1 dav dd digital power supply in a/d converter 2 vrt2 o a/d converter reference voltage (high side) for s-video chroma signal 3 vin6 i s-video 2 chroma signal (c-2) input pin (leave open or connect to agnd when not used) 4 vin5 i composite-5 or s-video 1 chroma signal (c-1) input pin (leave open or connect to agnd when not used) 5av dd analog power supply 6 agnd analog ground 7 adin2 i a/d converter input pin for s-video chroma signal 8 ampout2 o s-video chroma signal amp output 9 clpout2 o s-video chroma signal clamp voltage output 10 vrb2 o a/d converter reference voltage (low side) for s-video chroma signal 11 agnd analog ground 12 agnd analog ground 13 vrb1 i a/d converter reference voltage (low side) for composite/s-video (luminance signal) 14 clpout1 o composite/s-video (luminance signal) clamp voltage output 15 ampout1 o composite/s-video (luminance signal) amp output 16 adin1 i a/d converter input pin for composite/s-video (luminance signal) 17 vrcl1 i s-video (luminance signal) clamp voltage input 18 agnd analog ground 19 av dd analog power supply 20 vin4 i composite-4 input (leave open or connect to agnd when not used) 21 vin3 i composite-3 input (leave open or connect to agnd when not used) 22 vin2 i composite-2 s-video 2 luminance signal (y-2) input (leave open or connect to agnd when not used) 23 vin1 i composite-1 s-video 1 luminance signal (y-1) input (leave open or connect to agnd when not used) 24 vrt1 o a/d converter reference voltage (high side) for composite/s-video (luminance signal) 25 dav dd digital power supply in a/d converter 26 dagnd digital ground in a/d converter ? semiconductor msm7664 6/76 pedl7664-01 pin descriptions (continued) pin symbol type description 31 scan i not used. be left open or fixed at "0" (pulled down by internal resistor). 32 test[2] i not used. be left open or fixed at "0" (pulled down by internal resistor). 33 test[1] i not used. be left open or fixed at "0" (pulled down by internal resistor). 34 test[0] i not used. be left open or fixed at "0" (pulled down by internal resistor). 35 sleep i 0: normal operation, 1: sleep operation 36 reset_l i reset input pin (active "l"). after powering on, be sure to reset. 37 dv dd digital power supply 38 dgnd digital ground 39 scl i i 2 c-bus clock input 40 sda i/o i 2 c-bus data i/o pin 41 pllsel i not used. be left open or fixed at "0" (pulled down by internal resistor). 42 clksel i clock select input pin (pulled down by internal resistor). 0: double-speed input mode 1: normal input mode when a double-speed input mode is used, input a double frequency to system clock. 43 to 50 b[7] to b[0] o data output b[7]: msb, b[0]: lsb during rgb output mode: b 8-bit data output other than rgb output mode: hi-z output mode is set by pin 27 or 28, or register mra [7:6]. 51 dgnd digital ground 52 dv dd digital power supply 27 mode[0] i i/o switching input during external setting mode (pulled-down by internal resistors) 28 29 30 mode[1] mode[2] mode[3] internal/external pins are switched by register mra[0] the default of register mra[0] is external pin mode. mode [3:2] mode [1] input mode selection invalid if an itu-rbt.601 signal is input while the register mrc[7] is set to automatic ntsc/pal recognition. mode [0] input mode selection ntsc 4fsc can be set by register mra [3:1] only. output mode selection 00: itu-rbt.656 (with 8-bit ycbcr sav, eav, blank processing) 01: 8-bit (ycbcr) 10: 16-bit (ycbcr) (itu-rbt.601) 11: 24-bit rgb 0: ntsc 1: pal 0: itu-rbt.601 1: square pixel i i i ? semiconductor msm7664 7/76 pedl7664-01 pin descriptions (continued) pin symbol type description 53 to 60 y[7] to y[0] o data output y[7]: msb, y[0]: lsb during itu-rbt.656 output mode: ycbcr 8-bit data output during 8-bit (ycbcr) output mode: ycbcr 8-bit data output during 16-bit (ycbcr) output mode: y 8-bit data output during 24-bit rgb output mode: g 8-bit data output output mode is set by pin 27 or 28, or register mra [7:6]. 61 dv dd digital power supply 62 dgnd digital ground 63 to 70 c[7] to c[0] o data output c[7]: msb, c[0]: lsb during itu-rbt.656 output mode: hi-z during 8-bit (ycbcr) output mode: hi-z during 16-bit (ycbcr) output mode: cbcr 8-bit data output during 24-bit rgb output mode: r 8-bit data output output mode is set by pin 27 or 28, or register mra [7:6]. 71 odd/even o field display output if field is odd, "h" is output. 72 hvalid o horizontal valid pixel timing output pin if section is valid, "h" is output. 73 vvalid o vertical valid line timing output pin if section is valid, "h" is output. 74 vsync_l o vertical sync signal (v sync) output pin 75 hsync_l o horizontal sync signal (h sync) output pin 76 clkxo o pixel clock output during double-speed input mode (pin 42 = 0): one half of system clock frequency is output. during normal input mode (pin 42 = 1): the same frequency as system clock frequency is output. 77 clkx2o o system clock output system clock input is directly output. 78 dgnd digital ground 79 dv dd digital power supply 80 clkx2 i system clock input (selected by operation mode) ntsc itu-rbt.601 ntsc square pixel ntsc 4fsc pal itu-rbt.601 pal square pixel normal input mode 13.5 mhz 12.272727 mhz 14.31818 mhz 13.5 mhz 14.75 mhz double-speed input mode 27 mhz 24.545454 mhz 28.63636 mhz 27 mhz 29.5 mhz ? semiconductor msm7664 8/76 pedl7664-01 pin descriptions (continued) pin symbol type description 82 status[2] o status signal output selected by internal register omr[1] omr[1]: 0 omr[1]: 1 83 status[1] o vbi interval multiplex signal detection output 0: non-detection, 1: detection 84 m[7] o field memory control signal; re output 85 m[6] o field memory control signal; we output 86 m[5] o field memory control signal; rstr output 87 m[4] o field memory control signal; rstw output 88 m[3] o test output pin, normally "l" output 89 m[2] i i 2 c-bus slave address select 0: 1000001x 1: 1000011x (no internal pull-up or pull-down resistor) 90 m[1] i pin for setting by either external pin or internal register in order to select analog unit gain value (mgc) and video signal input pin. (no internal pull-up or pull-down resistor) 0: external pin mode gain value setting: pins 94 to 96 (gains[2:0]) are used input pin setting: pins 97 to 99 (ins[2:0]) are used 1: register mode gain value setting: register adc2[6:4] input pin setting: register adc1[2:0] internal register setting is invalid when external pin mode is set. 91 m[0] i selection of external field memory control signal output if field memory is not used, set m[0] to 0. 0: m[7:4] outputs are invalid 1: m[7:4] outputs are valid 92 dgnd digital ground 93 dv dd digital power supply ntsc-pal recognition (default) 0: ntsc, 1: pal hlock sync detection output 0: non-detection, 1: detection 81 status[3] o status signal output selected by internal register omr[0] omr[0]: 0 omr[0]: 1 fifo overflow detection (default) 0: non-detection, 1: detection csync output ? semiconductor msm7664 9/76 pedl7664-01 pin symbol type description 94 gains[2] i inputs for amplifier gain switch setting during external setting mode 97 ins[2] i inputs for signal input pin switch setting during external setting mode 100 dagnd digital ground in a/d converter 95 gains[1] 96 gains[0] external pin mode: pin 90 (m[1]) = 0 (pulled down by internal resistors) gains[2:0] [000] [001] [010] [011] [100] [101] [110] [111] gain value (x times) 1.00 1.35 1.75 2.30 3.00 3.80 5.00 undefined 98 ins[1] 99 ins[0] external pin mode: pin 90 (m[1]) = 0 (pulled down by internal resistors) ins[2:0] [000] [001] [010] [011] [100] [101] [110] [111] input pin vin1 (pin 23) composite-1 vin2 (pin 22) composite-2 vin3 (pin 21) composite-3 vin4 (pin 20) composite-4 vin5 (pin 4) composite-5 vin1 (pin 23) y-1 vin5 (pin 4) c-1 vin2 (pin 22) y-2 vin6 (pin 3) c-2 prohibited setting (adc enters sleep state) i i i i pin descriptions (continued) ? semiconductor msm7664 10/76 pedl7664-01 absolute maximum ratings parameter power supply voltage input voltage power consumption storage temperature symbol v dd v i p w t stg condition ta = 25?c v dd = 3.3 v rating C0.3 to +4.5 C0.3 to +5.5 1 C55 to +150 unit v v w c recommended operating conditions parameter power supply voltage power supply voltage digital "h" level input voltage digital "l" level input voltage symbol v dd gnd v ih1 v il condition typ. 3.3 0 unit v v v v operating temperature ta c min. 3.0 2.2 0 0 max. 3.45 v dd (*2) v ih2 (*1) v 0.8 v dd v dd (*2) 0.8 60 analog video signal input v ain sync tip to white peak level v p-p 0.8 1.1 *1: clksel, sda, clkxo *2: since the inputs have a tolerance of up to 5.5 v, it is possible to apply 5 v to the inputs. ? semiconductor msm7664 11/76 pedl7664-01 electrical characteristics dc characteristics parameter symbol v oh condition i oh = C6 ma (*2) i ol = 6 ma (*2) typ. unit "l" level output voltage v ol v min. 0.7 v dd 0 max. v dd 0.4 "h" level output voltage v input leakage current i i v i = gnd to v dd m a m a C10 +10 output leakage current i o v i = gnd to v dd m a C10 +10 sda output voltage sdav l i ol = 4 ma v 0 0.4 sda output current sdai o ma 3 i oh = C4 ma (*1) i ol = 4 ma (*1) r pull_down = 20 250 50 k w (*3) (ta = 0 to +70c, v dd (dv dd , adv dd , av dd ) = 3.0 to 3.45 v) *1: hsync_l, vsync_l, syssel, c[7:0], b[7:0], odd, vvalid, hvalid, clkxo, hsy, m[7:0] *2: y[7:0], clkx2o *3: mode[3:0], scan, test[2:0], pllsel, clksel, gains[2:0], ins[2:0] dc characteristics (analog unit) parameter symbol condition typ. unit min. max. ampout output voltage v oamp r o = 300 w v 0.3 2.4 clpout output voltage v oclp r o = 5 k w v 0.2 1.6 vrt output voltage v rt (*) 2.3 v 1.95 2.5 vrb output voltage v rb (*) 0.3 v 0.15 0.4 adin v iadin v v rb v rt vin v ivin capacitive coupling v p-p 0.4 1.3 input current i ivin v i = 1.5 v m a 530 (ta = 0 to +70c, v dd (dv dd , adv dd , av dd ) = 3.0 to 3.45 v, gnd = 0 v) *: 10 k w connected between v rt and v rb dc characteristics parameter symbol condition typ. unit min. max. power supply current (operating) i d1 ad1 on ad2 off clkx2 = 27 mhz 190 ma 120 260 power supply current (operating) i d2 ad1 on ad2 on clkx2 = 27 mhz 200 ma 120 275 power supply current (sleep) i doff v i = 1.5 v ma 05 (ta = 0 to +70c, v dd (dv dd , adv dd , av dd ) = 3.0 to 3.45 v, gnd = 0 v) ? semiconductor msm7664 12/76 pedl7664-01 ac characteristics (double speed mode) parameter symbol condition min. typ. max. unit clkx2 cycle frequency 1/t clkx2 itu-rs601 27.0 mhz ntsc 4fsc 28.63636 mhz ntsc square pixel 24.545454 mhz pal square pixel 29.5 mhz output data delay time 1 (*) t od21 clksel : l 7 (5) 26 (24) ns output data delay time 2 (*) t od22 clksel : l 6 (4) 22 (20) ns t cxd21 clksel : l 5 20 ns output clock delay time (*) (clkx2-clkx2o) t cxd22 clksel : l 4 17 ns (*) output load: 40 pf values in the parentheses indicate the delay time when 8-bit ycbcr format data is output from the y pin. the clock frequenc y accurac y is within 100 ppm. scl clock cycle time t c_scl r pull_up = 4.7 k w 200 ns scl low level cycle t l_scl r pull_up = 4.7 k w 100 ns output clock delay time (*) (clkx2-clkxo) (ta = 0 to +70c, v dd (dv dd , adv dd , av dd ) = 3.0 to 3.45 v, gnd = 0 v) clkx2 duty t d_d2 4555% output data delay time 3 (*) t od23 clksel : l 7 (5) 30 (28) ns output data delay time 1x1 (*) t odx21 clksel : l 2 8 ns output data delay time 1x2 (*) t odx22 clksel : l 1 5 ns output data delay time 1x3 (*) t odx23 clksel : l 2 10 ns output data delay time 2x1 (*) t od2x21 clksel : l 3 (1) 11 (9) ns output data delay time 2x2 (*) t od2x22 clksel : l 2 (1) 9 (7) ns output data delay time 2x3 (*) t od2x23 clksel : l 3 (1) 13 (11) ns reset_l width t rst_w 200 ns ? semiconductor msm7664 13/76 pedl7664-01 ac characteristics (single speed mode) parameter symbol condition min. typ. max. unit clkx2 cycle frequency 1/t clkx2 itu-rs601 13.5 mhz ntsc 4fsc 14.31818 mhz ntsc square pixel 12.272727 mhz pal square pixel 14.75 mhz output data delay time 1 (*) t od11 clksel : h 8 26 ns output data delay time 2 (*) t od12 clksel : h 7 22 ns t cxd11 clksel : h 6 20 ns output clock delay time (*) (clkx2-clkx2o) t cxd12 clksel : h 5 17 ns (*) output load: 40 pf the clock frequenc y accurac y is within 100 ppm. scl clock cycle time t c_scl r pull_up = 4.7 k w 200 ns scl low level cycle t l_scl r pull_up = 4.7 k w 100 ns output clock delay time (*) (clkx2-clkxo) (ta = 0 to +70c, v dd (dv dd , adv dd , av dd ) = 3.0 to 3.45 v, gnd = 0 v) clkx2 duty t d_d1 clksel : h 40 60 % output data delay time 3 (*) t od13 clksel : h 8 30 ns output data delay time 1x1 (*) t odx11 clksel : h 2 8 ns output data delay time 1x2 (*) t odx12 clksel : h 1 5 ns output data delay time 1x3 (*) t odx13 clksel : h 2 12 ns output data delay time 2x1 (*) t od2x11 clksel : h 3 11 ns output data delay time 2x2 (*) t od2x12 clksel : h 2 8 ns output data delay time 2x3 (*) t od2x13 clksel : h 3 15 ns reset_l width t rst_w 200 ns ? semiconductor msm7664 14/76 pedl7664-01 input and output timing clock and output timing data delay (when a standard signal is input) the data delay is equal to the blank delay. 1h depends on the sampling mode. the numeric value (t value) may be changed according to a signal state. since the output period is fixed during fifo mode, the amount of delay is changed. if y/c separation is performed using trap filter during pal mode, 1h is not added. t = 1 pixel rate, a = absorption difference video mode input signal fifo/fm mode amount of delay ntsc composite fifo-1 1h + 358t a ntsc composite fm 1h + 358t pal composite fifo-1 1h + 358t a pal composite fm 1h + 358t ntsc, pal s-video fifo-1 358t a ntsc, pal s-video fm 358t clkx2o clkx2 clkxo t cxd21 t cxd11 t cxd22 t cxd21 t clkx1 clksel: l y[7:0], c[7:0] b[7:0] t clkx2 t od11 t od21 t od12 t od22 t od2x11 t od2x21 t odx11 t odx21 t od2x12 t od2x22 t odx12 t odx22 t od13 t od23 t od2x13 t od2x23 t odx13 t odx23 hvalid, vvalid, odd hsync_l, vsync_l status[3:1] m[7:4] clksel: h data delay analog video in decoder output blank blank delay active data ? semiconductor msm7664 15/76 pedl7664-01 i 2 c-bus interface input/output timing the basic input/output timing of the i 2 c-bus is indicated below. 12 789 ack 12 3-8 9 ack s start condition p stop condition data line stable: data valid change of data allowed scl sda msb t c_scl i 2 c-bus timing the i 2 c-bus timing conforms to this table. however, the i 2 c-bus can operate faster than at the speeds, specified above. actually, the scl frequency is up to about 5 mhz. the hold time and setup time in that case must conform to the ratio described in the above table. symbol parameter min. unit f scl scl frequency 0 khz t buf bus open period 4.7 m s t hd: sta start condition hold time 4.0 m s t low clock low period 4.7 m s t high clock high period 4.0 m s t su: sta start condition setup time 4.7 m s t hd: dat data hold time 300 ns t su: dat data setup time 250 ns t r line rise time m s t f line fall time ns t su: sto stop condition setup time 4.7 m s 100 1 300 max. s p scl sda t bfu t hd:sta sp t low t hd:dat t r t f t hd:sta t high t su:dat t su:sta t su:sto ? semiconductor msm7664 16/76 pedl7664-01 functional description analog unit 1) analog input select: compatible with composite video signals and s-video signals. input selection can be switched by register control via the i 2 c-bus or by external pins. (see the below chart for pin combinations.) when the lsi is used in composite video mode, input clocks or do resetting after setting s-video mode (101), (110) before setting composite video mode. 2) clamp function: an analog clamp and a digital pulse clamp can be used. analog clamp analog clamp ? digital clamp (hybrid clamp) digital clamp only the digital clamp can be set as the pedestal clamp. # related register mrb[3:2] 3) agc amp: the agc function operates depending upon the input level. manual gain setting is also possible. this agc function operates at 2 stages, the analog unit and digital unit. digital decoded data is output in conformance with itu-rbt.601. refer to the explanation of m[1] pin (pin 90). # related register adc2[6:4] 4) a/d converter: two internal 8-bit a/d converters sample at twice the pixel frequency. (sampling at the pixel frequency is possible by changing the register setting.) # related register adc1[2:0] list of analog input conditions input signal control pin input pin adc selection ins[2:0] vin1 vin2 vin3 vin4 vin5 vin6 on off composite-1 input* [000] composite on off composite-2 input [001] composite on off composite-3 input [010] composite on off composite-4 input [011] composite on off composite-5 input [100] composite on off s-video-1 input [101] luminance chroma on on s-video-2 input [110] luminance chroma on on all inputs off [111] off (sleep) off off register adc1[2:0] [000] [001] [010] [011] [100] [101] [110] [111] blank spaces: non-selectable, *: register default setting after lsi reset m[1] pin setting, 0: external mode, 1: internal register mode ? semiconductor msm7664 17/76 pedl7664-01 manual gain control (analog amp gain) gain setting pins gains[2:0] set gain value typ. value (multiplication factor) [000] 1.0 [001] 1.35 [010] 1.75 [011] 2.3 [100] 3.0 [101] 3.8 [110] 5.0 [111] undefined register adc2[6:4] [000] [001] [010] [011] [100] [101] [110] [111] ? semiconductor msm7664 18/76 pedl7664-01 decoder unit 1. prologue block the prologue block inputs data and performs y/c separation. data can be input at either the pixel frequency (itu-rbt.601: 13.5 mhz) or at twice the pixel frequency (itu-rbt.601: 27 mhz). if input at twice the pixel frequency, data is processed after passing through a decimator circuit to convert it to the pixel frequency. the decimator circuit may be bypassed by changing the register setting, regardless of whether data is input at the normal pixel frequency or at twice the pixel frequency. if a composite signal (cvbs) is input, the default setting performs y/c separation using a 2- dimensional adaptive comb filter. the following operating modes can be selected via the i 2 c-bus. default settings are indicated by an asterisk (*). the default state is selected at reset. 1) video input mode selection (related register mrc[7]) ntsc/pal auto-select* (only for itu-rbt.601) dependent upon operating mode selected when itu-rbt.601 is selected, the video input mode is automatically set depending upon the number of lines per field. 2) operating mode selection (related register mra[3:1]) ntsc itu-rbt.601 13.5 mhz* ntsc square pixel 12.272727 mhz ntsc 4fsc 14.31818 mhz pal itu-rbt.601 13.5 mhz pal square pixel 14.75 mhz even if input at twice the pixel frequency, the internal processing is performed at the pixel frequency. 3) decimator circuit pass/bypass selection (related register mrc[4]) pass through decimator circuit* bypass decimator circuit compatible only when input at twice the pixel frequency. 4) y/c separation mode selection (related register mrb[1:0]) use adaptive comb filter* use non-adaptive comb filter do not use comb filter (use trap filter) the adaptive comb filter for a ntsc signal makes the correlation between up to 3 consecutive lines, and y/c separation is performed by the 3-line or 2-line comb filter according to the format of correlation. the adaptive comb filter for a pal signal makes the correlation between only 2 lines and performs y/c separation by switching between the 2-line comb filter and trap filter. at that time, the adaptive transition method is employed in which the filter is gradually switched depending on the level of correlation. the non-adaptive comb filter performs y/c separation by removing the luminance component based on the average of preceding and following lines (when there is correlation between 3 lines). (the average of 2 lines in the case of a pal signal) when a comb filter is not used, y/c separation is performed by a trap filter. ? semiconductor msm7664 19/76 pedl7664-01 if an s-video signal is input, these y/c separation circuits are bypassed. the functions of this block only operate when lines are valid as image information. during the v blanking interval, cvbs signals are not processed. 2. luminance block the luminance block removes synchronous signals from signals containing luminance components after y/c separation. the signals are compensated and then output as luminance signals. two modes of gain control functions can be selected for the luminance signal output level: agc (auto gain control) and mgc (manual gain control). in the agc mode, luminance level amplification is determined by comparing the sync depth with a reference value. the default is 40ire and can be changed by the register setting. the input has a sync tip clamp. in the mgc mode, the signal amplification and black level can be changed by register settings. this block can select the follwing operating modes. 1) selection of luminance level limiter usage (related register lumc[7]) do not use* use when a limiter is used, the luminance level is limited to 16 to 235. 2) selection of prefilter and sharp filter usage (related register lumc[6]) do not use* use these filters are used to enhance the edges of luminance component signals. two filters operate in pairs. for their characteristics, refer to filter characteristics described later. 3) selection of aperture bandpass filter coefficient (related register lumc[5:4]) middle range* high range 4) coring range selection (related register lumc[3:2]) off* 4lbs 5lbs 7lbs 5) aperture weighting coefficient selection (related register lumc[1:0]) 0* 0.25 0.75 1.50 both coring and aperture compensation processes perform contour compensation. 6) selection of pixel position compensating circuit usage (related register mrc[6]) use* do not use ? semiconductor msm7664 20/76 pedl7664-01 7) agc loop filter time constant selection (related register agclf[7:6]) slow convergence time 903 ms medium 225 ms* fast 56 ms mgc mode 0 these are designed times from the input gain being rapidly lowered to 50% (C6 db) of the value at a stable state when normal signals are input till the output being returned to C1 db (actually these times differ depending on the signal state). mgc mode: manual gain setting is possible by register agclf[5:0] set the ssepl[7] value to a 0 when the mgc mode is used. 8) parameter for fine adjustment of agc sync depth (related register agclf[5:0]) agc reference level is changed. 9) parameter for fine adjustment of sync removal level (related register ssepl[6:0]) the black level is adjusted. the default setting outputs the pedestal position as a black level (=16). 10)pedestal clamp selection (related register ssepl[7]) do not use pedestal clamp* use pedestal clamp (at this time, agc does not operate, mgc operates) 3. chrominance block this block processes the chroma signals. the following operating modes can be selected. 1) selection of chroma bandpass filter usage (related register chrc[2]) do not use* use 2) acc loop filter time constant selection (related register acclf[6:5]) fast2 convergence time 27 ms medium 424 ms* fast 106 ms mcc mode 0 these are designed times from the input gain being rapidly lowered to 50% (C6 db) of the value at a stable state when normal signals are input till the output being returned to C1 db (actually these times differ depending on the signal state). mcc mode: manual gain setting is possible by register acclf[4:0] 3) acc reference level fine adjustment (related register acclf[4:0]) acc reference level is changed. 4) parameter for burst level fine adjustment (related register chrc[1:0]) threshold level at which chroma amplitude becomes valid is selected based upon color burst ratio. 0.5 0.25* 0.125 off off: the color killer function is turned off. if decoloration occurs while decoding a still picture, setting the threshold level to "off" will reduce the decoloration. 5) color killer mode selection (related register mrb[5]) auto color killer mode* forced color killer 6) parameter for fine adjustment of color subcarrier phase (related register hue[7:0]) hue control function ? semiconductor msm7664 21/76 pedl7664-01 7) vertical color filter (related register chrc[6:4]) averaging computation is made for the lines before and after the u, v demodulated signal. this is likely to make the image appear smooth. using a register, it is possible to select the modes of either to carry out or not carry out the averaging operation based on the correlation between the previous and next lines, or not to carry out the averaging operation at all. in addition, it is also possible to change the level of judging the correlation using a register setting. in this block, chroma signals pass through a bandpass filter to cut out unnecessary band. to maintain a constant chroma level, these signals then pass through an acc compensating circuit and are uv demodulated. (the filter can be bypassed.) if the demodulated result does not reach a constant level, color killer signals are generated to fix the acc gain. this functions as an auto color killer control circuit. the uv demodulated results pass through a low-pass filter and are output as chrominance signals. 4. synchronization block this block processes the sync signals. synchronous signals are generated for chip output and for internal use. various signals are output from this block and the following operating modes can be selected. 1) adjustment of sync threshold level (internal sync) (related register sthr[7:0]) sync detection level is set. 2) fine adjustment of hsy (horizontal sync clamp) signal (related registers hsyt[7:4], hsyt[3:0], mrb[3:2]) 2-1) fine adjustment of hsy signal (start side) 2-2) fine adjustment of hsy signal (stop side) the hsy signal provides the sync-tip and clamp timing to the a/d converter. this signal is used for digital clamp, but can not be observed from outside. 3) fine adjustment of hsync_l signal (related register hsdl[7:0]) hsync_l signal output position is adjusted. 4) hvalid control (related registers hvalt[7:4], hvalt[3:0]) 4-1) fine adjustment of hvalid signal (start side) 4-2) fine adjustment of hvalid signal (stop side) data signals are transferred at the rising edge of the hvalid signal. 5) vvalid control (related registers vvalt[7:4], vvalt[3:0]) 5-1) fine adjustment of vvalid signal (start side) 5-2) fine adjustment of vvalid signal (stop side) 6) fifo and field memory mode selection (related register mrb[7:6]) fifo-1 mode*: sets and outputs a standard value for the number of pixels per 1h from the internal fifo. this mode is also compatible (to a degree) with non-standard vtr signals. fifo-2 mode: sets and outputs a constant pixel number corresponding to the input h interval for the number of pixels per 1h from the internal fifo. ? semiconductor msm7664 22/76 pedl7664-01 fm-1 mode: this mode outputs the decoded results according to the sync signal. usage of external field memory is required to manage the number of pixels and to absorb jitter. memory control signals are to be generated externally. fm-2 mode: this mode is compatible with considerably distorted non-standard vtr signals. jitter is absorbed by using external field memory (2 mb 2) and the standard value is set as the pixel number. field memory control signals are output simultaneously from m[7:4]. 7) field memory control signals if the fm-2 mode uses external field memory (2 mb 2) instead of the internal fifo, field memory control signals are supplied from pins m[7:4]. at this time, pin m[0] requires to be set to "h". 5. epilogue block the epilogue block outputs the uv signal from the chrominance block and the y signal from the luminance block in a format based on a signal obtained from the control register setting. this block can select the following modes. 1) output mode selection (related register mra[7:6]) 1-1) itu-rbt.656 (sav, eav, blank processing) 1-2) * 8-bit (ycbcr) output (2x pixel clock) synchronization with hsync_l, vsync_l 1-3) 16-bit (8-bit y/8-bit cbcr) (pixel clock) synchronization with hsync_l, vsync_l 1-4) 24-bit rgb (8 bits each) synchronization with hsync_l, vsync_l 2) enable blue back display when synchronization fails (related register mrb[4]) off on* 3) selection of ycbcr signal output format (related register mrc[5]) ycbcr 4 : 2 : 2* ycbcr 4 : 1 : 1 the chrominance signal (u, v component) outputs cb and cr data to the c pin in an output format to be described later. 4) output pin enable selection (related registers omr[2], misc[1:0]) high-impedance output enable* pins that become high impedance are determined by setting. see "output pin control table" described later. 5) various mode detection (related register omr[1:0]) ntsc/pal detection multiplex signal detection hsync synchronization detection internal fifo overflow detection 6) output signal phase control (related registers opcy[1:0], opcc[1:0]) y and c phases can each be adjusted in the range of C2 to +1 pixels. ? semiconductor msm7664 23/76 pedl7664-01 6. vbid block the vbid block detects agc, cc, wss and cgms data from the input luminance signal and holds them. the vbid module consists of the following four modules. the detection line and detection level can be changed by setting of the register. 1) agc module this module detects whether the macrovision agc pulse (ntsc/pal) is included in the specified line. if the agc pulse has been detected in the specified lines, the flag is set. ntsc-specified lines: 12 to 19 odd-numbered lines 275 to 282 even-numbered lines pal-specified lines: 9 to 18 odd-numbered lines 321 to 330 even-numbered lines 2) c.c. (closed caption) module this module detects whether the closed caption data (ntsc/pal) is included in the specifed lines. if it has been detected in the specified lines, character data on the odd number lines and character data on the even number lines are individually held and flags are set for each data separately. ntsc-specified lines: 21 odd-numbered lines 284 even-numbered lines pal-specified lines: 22 odd-numbered lines 3350 even-numbered lines 3) wss (wide screen signalling) module this module detects wss data on the lines specified by ntsc. if it has been detected, the flag is set. (pal only) pal-specified lines: 23 lines 4) cgms module this module detects cgms data on the lines specified by iec61880. if is has been detected, the flag is set (ntsc only) ntsc-specified lines: 20 odd-numbered lines 283 even-numbered lines 7. i 2 c control block this serial interface block is based on the i 2 c standard of the phillips corporation. the registers at up to subaddress hex14 are write-only registers and the register at subaddress hex20 is a read-only register. the license to use the lsi chip for i 2 c systems is granted on the basis of the i 2 c patent of the phillips corporation by purchasing the lsi chip. 8. test control block this block is used to test the lsi chip. normally this block is not used. ? semiconductor msm7664 24/76 pedl7664-01 input signal level the figure below shows the recommended range of the input signal, received in an 8-bit straight binary format. reserved 255 iuminance 200 sync ntsc:60 (pal:63) 4 0 chrominance +dc input black level 13 246 input sync-tip level ntsc/pal; cvbs[7:0] input range the above input conditions are ideal. because analog signals are normally input at different levels, the exact settings described above are difficult to achieve. while maintaining the ratio of white peak (100%)/sync = 100ire/40ire (ntsc), if the input signal is set within the a/d converter's voltage range/the y digital output will be output by digital agc operation with the pedestal position set at the black level (16) and the white peak position (100%) set at the peak level (235) even if the peak level does not reach 196 (200 C 4). ? semiconductor msm7664 25/76 pedl7664-01 output format itu-rbt.656 output, 8-bit (ycbcr) output, and 16-bit (8-bit y/8-bit cbcr) output have the following formats. the ycbcr 4:2:2 format and 4:1:1 format are shown below. the output format can be changed by register settings. pixel byte sequence output y7 (msb) y6 y5 y4 y3 y2 y1 y0 (lsb) y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 c7 (msb) c6 c5 c4 c3 c2 c1 c0 (lsb) cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0 cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 y point 0 2 ycbcr 4:2:2 format 345 1 c point 0 2 4 pixel byte sequence output y7 (msb) y6 y5 y4 y3 y2 y1 y0 (lsb) y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 c7 (msb) c6 c5 c4 c3 c2 c1 c0 (lsb) cb7 cb6 cr7 cr6 0 0 0 0 cb5 cb4 cr5 cr4 0 0 0 0 y point 0 2345 1 c point 0 4 ycbcr 4:1:1 format y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 67 cb7 cb6 cr7 cr6 0 0 0 0 cb5 cb4 cr5 cr4 0 0 0 0 cb3 cb2 cr3 cr2 0 0 0 0 cb1 cb0 cr1 cr0 0 0 0 0 cb3 cb2 cr3 cr2 0 0 0 0 cb1 cb0 cr1 cr0 0 0 0 0 ? semiconductor msm7664 26/76 pedl7664-01 timing description vertical synchronizing signal the vertical synchronizing signal timing is as follows. the default output is as shown below, but the internal processing of the synchronizing signal is performed before 1h. 524525123456789 2122 cvbs hvalid hsync_l vsync_l vvalid odd 262 263 264 265 266 267 268 269 270 271 283 284 285 cvbs hvalid hsync_l vsync_l vvalid odd csync_l csync_l vertical synchronizing signal (60 hz) ? semiconductor msm7664 27/76 pedl7664-01 621622623624625123456 2324 cvbs hvalid hsync_l vsync_l vvalid odd 309 310 311 312 313 314 315 316 317 318 336 337 338 cvbs hvalid hsync_l vsync_l vvalid odd csync_l csync_l vertical synchronizing signal (50 hz) ? semiconductor msm7664 28/76 pedl7664-01 a/d converter support signal the waveform of the hsy signal, shown below, provides clamp timing to the a/d converter when hsy clamp (digital clamp) is selected. the start and end edges of the clamp pulse have a variable range from the sync tip to the pedestal position. (hsy is an internal signal.) color burst cvbs burst hsy pedestal sync tip a/d converter support signal output timing ? itu-rbt.656 output 4t digital line {1716t (ntsc, 525), 1728t (pal, 625)} digital active line digital line blanking 276t (ntsc, 525) 288t (pal, 625) multiplexed video data cb0 y00 cr0 cb1 y10 cr1 y11 video data block (1440t) eav 4t sav eav t sav eav : clock periods 37 ns normal (1/27 mhz) : start of active video timing reference code : end of active video timing reference code itu-rbt.656 output (data in one line in which video data presents) during the blanking interval, data is output with the y value. note: digital line 1716t (ntsc, 525) and 1728t (pal, 625) are not maintained at the next line. digital active line 1440t of the line immediately after vvalid falls and the 10th or 11th line after vsync_l rises will fluctuate due to pixel compensation. especially when a non-standard signal is input, the line immediately after vvalid falls will fluctuate largely due to instability of the input signal. due to phenomena such as an increase in the number of lines for a standard signal and a decrease in the number of lines for a non- standard signal, it may not be possible to guarantee correct eav and sav functionality. ? semiconductor msm7664 29/76 pedl7664-01 contents of sav and eav both sav and eav consist of 4 words. their configuration is shown below. word bit no. f = 0: during field 1 1: during field 2 v = 0: elsewhere 1: during field blanking h = 0: sav h = 1: eav 7 (msb) 654321 0 (lsb) first 11111111 second 00000000 third 00000000 fourth p3, p2, p1, p0: protection bit 1 f v h p3 p2 p1 p0 the 4th word of sav and eav the relationship between the f, v, h and protection bits in the 4th word of sav and eav is shown below. bit no. 7 (msb) 6543210 function fixed 1 f v h p3 p2 p1 p0 010000000 110011101 210101011 310110110 411000111 511011010 611101100 711110001 usually, v = 1 during blanking, however when vbi data is detected and v = 0 is the desired output, set the mrc[3] sav, eav v-status of mode register c (mrc) to "1". ? semiconductor msm7664 30/76 pedl7664-01 cb0 y[7:0] hvalid clkx2 y0 cr0 y1 cb2 y2 cr2 y3 cb4 cr nC4 y nC3 cb nC2 y nC2 cr nC2 y nC1 8-bit (ycbcr: 2x clock) output y0 y1 y2 y3 y(nC2) y(nC1) y[7:0] hvalid clko clkx2 cb0 cr0 cb2 cr2 cb(nC2) cr(nC2) c(7:0) 16-bit (y: 8-bit, cbcr: 8-bit) output r0 r1 r2 r3 r(nC2) r(nC1) r[7:0] hvalid clko clkx2 g0 g1 cb2 cr3 g(nC2) g(nC1) g[7:0] b0 b1 b2 b3 b(nC2) b(nC1) b[7:0] 24-bit (r: 8-bit, g: 8-bit, b: 8-bit) output output data format note: when a single-speed clock (13.5 mhz, etc.) is input in 16-bit or 24-bit (rgb) output mode, the waveform of clkx2 changes to a single speed waveform, but the format after that is not changed. ? semiconductor msm7664 31/76 pedl7664-01 ? timing when using external field memory field memory timing in the fm-2 mode, using control signals from the decoder field memory: msm51v8222, 2 units are used (y and c) four memory control signals are supplied from the decoder, m[4]: rstw, m[5]: rstr, m[6]: we:, and m[7]: re. ntsc signal (13.5 mhz) hsync_l 1 35 2345678910111213141516171819202122232425262728293031323334 vsync_l hvalid vvalid odd-even y (7:0) c (7:0) rstw we hsync_l vsync_l hvlid vvalid odd/even re rstr y (7:0) c ( 7:0 ) ntsc: odd field hsync_l 1 35 2345678910111213141516171819202122232425262728293031323334 vsync_l hvalid vvalid odd-even y (7:0) c (7:0) rstw we hsync_l vsync_l hvlid vvalid odd/even re rstr y (7:0) c ( 7:0 ) ntsc: even field ? semiconductor msm7664 32/76 pedl7664-01 pal signal (13.5 mhz) hsync_l 1 39 2345678910111213141516171819202122232425263132333435363738 vsync_l hvalid vvalid odd-even y (7:0) c (7:0) rstw we hsync_l vsync_l hvlid vvalid odd/even re rstr y (7:0) c (7:0) pal: odd field hsync_l 1 38 2345678910111213141516171819202122232425262731323334353637 vsync_l hvalid vvalid odd-even y (7:0) c (7:0) rstw we hsync_l vsync_l hvlid vvalid odd/even re rstr y (7:0) c (7:0) pal: even field ? semiconductor msm7664 33/76 pedl7664-01 horizontal synchronizing signal the horizontal synchronizing signal timing is shown below. y[7:0] hvalid hsync_l 60 pixels front-porch hsync back-porch relation between video mode and pixel number (default settings when standard signal is input) video mode pixel type pixel rate (mhz) total pixels active pixels front- porch hsync back- porch hblk total iturbt.601 13.5 858 720 16 122 138 ntsc square pixel 12.272727 780 640 28 112 140 4fsc 14.31818 910 768 8 134 142 pal iturbt.601 13.5 864 720 12 132 144 square pixel 14.75 944 768 34 142 176 horizontal timing ? semiconductor msm7664 34/76 pedl7664-01 hvalid vvalid 0 2t t = 1/13.5 mhz hsync_l hvalid 138 pixels 60 pixels 16 pixels hsync_l vsync_l odd (odd) odd ( even ) 0 about 10.4 m s about 21.6 m s synchronizing signal timing (default timing when standard signal is input) ? semiconductor msm7664 35/76 pedl7664-01 vbi data detection (when an s-video signal is input): status1 timing vbi data detection results are output from the status1 pin. results of individual data detection are read from the register. video in y[7:0] hsync_l hvalid status1 detection level 80 to 136 vbi data detection (when a composite signal is input): status1 timing vbi data detection results are output from the status1 pin. results of individual data detection are read from the register. video in y[7:0] hsync_l hvalid status1 detection level 80 to 136 ? semiconductor msm7664 36/76 pedl7664-01 i 2 c bus format the i 2 c-bus interface input format is shown below. slave address (w) s subaddress a slave address (r) a a data 20 a' read mode slave address (w) s subaddress a data 0 a a ...... data n a p write mode s data m a' p slave address (w) s subaddress (1f) a reset data a a p read mode 2 (vbid read) slave address (w) s subaddress (21) a slave address (r) a a data 21 a' s ...... data m a p hereafter the above operations are repeated. ...... - - a - ? semiconductor msm7664 37/76 pedl7664-01 as mentioned above, the write/read operation can be executed from subaddress to subaddress continuously. when the write/read operation is executed at subaddresses discontinuously, the acknowledge and stop condition formats are input repeatedly after data 0. data can be read at subaddress 0x20 only. the content of read register (vbid-related data) is held unless reset is instructed by the register at address 1f. the input format is shown in "read mode2". the equipment should return an acknowledge signal for read data. if one of the following matters occurs, the decoder will not return "a" (acknowledge). ? the slave address does not match. ? a non-existent subaddress is specified. ? the write attribute of a register does not match "x" (read ["1"]/write ["0"] control bit). the input timing is shown below. s start condition p scl sda 2 18 ack subaddress 2 18 ack data 2 18 ack stop condition slave address s slave address a, a' subaddress data n description start condition slave address 1000001x, 8th bit is write signal ["0"] or read signal ["1"] slave address is set at m[2] pin (pin 89). acknowledge. generated by slave subaddress byte data to write to address designated by subaddress. symbol p stop condition data m data to read from address designated by subaddress ? semiconductor msm7664 38/76 pedl7664-01 operating mode setting there are two types of video mode settings. 1. external pin mode: direct setting from dedicated pins 2. register setting mode: specification by internal register settings these modes can be switched by the mode register mra[0]. the reset state (default) is the external pin mode. the following registers can be set in the external pin mode. mra[7:6] output mode 00: itu-rbt.656 (sav, eav, blank processing) *01: 8 bit (ycbcr) hsync_l and vsync_l used for synchronization 10: itu-rbt.601 16 bit (8 bit y, 8 bit cbcr) 11: rgb (8 bit r, 8 bit g, 8 bit b) mra[3:1] sampling mode *000: ntsc itu-rbt.601 13.5 mhz (27.0 mhz) 001: ntsc square pixel 12.272727 mhz (24.545454 mhz) 010: ntsc 4fsc 14.31818 mhz (28.63636 mhz) 100: pal itu-rbt.601 13.5 mhz (27.0 mhz) 101: pal square pixel 14.75 mhz (29.5 mhz) note: 010: ntsc 4fsc cannot be set externally. pin setting example ntsc, 27 mhz (itu-rbt.601), composite input, 8-bit (ycbcr) output notes condition pin name 0 : itu-rbt.656 01 : 8-bit (ycbcr) = low mode[3] 10 : 16-bit (y + cbcr) 11 : rgb = high mode[2] 0 : ntsc 1 : pal = low mode[1] 0 : itu-rbt.601 1 : square pixel = low mode[0] 0 : twice the pixel frequency 1 : pixel frequency = low clksel = low pllsel = low ins[2:0] normally set to a low level = low gains[2:0] = low test[2:0] = low scan = low m[2] normally set to a low level = low m[1] = low m[0] 0 : normal operation 1 : sleep = low sleep : low = 1000001, : high = 1000011 ? semiconductor msm7664 39/76 pedl7664-01 internal registers register list d7 mra7 mrb7 hsyt7 d6 d5 d4 data byte d3 d2 d1 d0 sub- address register function mode register a (mra) mode register b (mrb) horizontal sync trimmer (hsyt) sthr7 sync threshold level adjust (sthr) hsdl7 horizontal sync delay (hsdl) hvalid7 horizontal valid trimmer (hvalt) vvalid7 vertical valid trimmer (vvalt) lumc7 luminance control (lumc) agclf7 agc/pedestal loop filter control (agclf) ssepl7 sync separation level (ssepl) chrc7 chrominance control (chrc) acclf7 acc loop filter control (acclf) hue7 hue control (hue) omr7 output phase control for data y (opcy) mra6 mrb6 hsyt6 sthr6 hsdl6 hvalid6 vvalid6 lumc6 agclf6 ssepl6 chrc6 acclf6 hue6 omr6 mra5 mrb5 hsyt5 sthr5 hsdl5 hvalid5 vvalid5 lumc5 agclf5 ssepl5 chrc5 acclf5 hue5 omr5 mra4 mrb4 hsyt4 sthr4 hsdl4 hvalid4 vvalid4 lumc4 agclf4 ssepl4 chrc4 acclf4 hue4 omr4 mra3 mrb3 hsyt3 sthr3 hsdl3 hvalid3 vvalid3 lumc3 agclf3 ssepl3 chrc3 acclf3 hue3 omr3 mra2 mrb2 hsyt2 sthr2 hsdl2 hvalid2 vvalid2 lumc2 agclf2 ssepl2 chrc2 acclf2 hue2 omr2 mra1 mrb1 hsyt1 sthr1 hsdl1 hvalid1 vvalid1 lumc1 agclf1 ssepl1 chrc1 acclf1 hue1 omr1 mra0 mrb0 hsyt0 sthr0 hsdl0 hvalid0 vvalid0 lumc0 agclf0 ssepl0 chrc0 acclf0 hue0 omr0 0 1 2 3 4 5 6 7 8 9 a b c d opcc7 output phase control for data c (opcc) opcc6 opcc5 opcc4 opcc3 opcc2 opcc1 opcc0 e f write write write write write write write write write write write write write write write write write /read adc17 optional mode register (omr) 10 write adc27 adc register (adc1) 11 write adc37 adc register (adc2) 12 write zld7 adc register (adc3) 13 write 0 level detect register (zld) 14 write mode register c (mrc) mrc7 mrc6 mrc5 mrc4 mrc3 mrc2 mrc1 mrc0 opcy7 opcy6 opcy5 opcy4 opcy3 opcy2 opcy1 opcy0 adc16 adc26 adc36 zld6 adc15 adc25 adc35 zld5 adc14 adc24 adc34 zld4 adc13 adc23 adc33 zld3 adc12 adc22 adc32 zld2 adc11 adc21 adc31 zld1 adc10 adc20 adc30 zld0 ycsc7 y/c separation circuit option register (ycsc) 15 write ycsc6 ycsc5 ycsc4 ycsc3 ycsc2 ycsc1 ycsc0 omrb7 optional mode register b (omrb) 16 write omrb6omrb5omrb4omrb3omrb2omrb1omrb0 ccd17 closed caption detected-1 register (ccd1) 17 write ccd16 ccd15 ccd14 ccd13 ccd12 ccd11 ccd10 ccd27 closed caption detected-2 register (ccd2) 18 write ccd26 ccd25 ccd24 ccd23 ccd22 ccd21 ccd20 cgms17 cgms detected-1 register (cgms1) 19 write cgms16 cgms15 cgms14 cgms13 cgms12 cgms11 cgms10 cgms27 cgms detected-2 register (cgms2) 1a write cgms26 cgms25 cgms24 cgms23 cgms22 cgms21 cgms20 agcd17 agc pulse detected-1 register (agcd1) 1b write agcd16 agcd15 agcd14 agcd13 agcd12 agcd11 agcd10 agcd27 agc pulse detected-2 register (agcd2) 1c write agcd26 agcd25 agcd24 agcd23 agcd22 agcd21 agcd20 wssd7 wss data detected register (wssd) 1d write wssd6 wssd5 wssd4 wssd3 wssd2 wssd1 wssd0 misc7 tri-state control of output-pin register (misc) 1e write misc6 misc5 misc4 misc3 misc2 misc1 misc0 aireg7 reset data request for vbid function register (aireg) 1f write aireg6aireg5aireg4aireg3aireg2aireg1aireg0 ? semiconductor msm7664 40/76 pedl7664-01 d7 ccde1 7 cgmso07 cgmso27 d6 d5 d4 data byte d3 d2 d1 d0 sub- address register function c. c. data buffer register in even field (ccde1) cgms data buffer register in odd field (cgms00) cgms data buffer register in odd field (cgms02) cgmse07 cgms data buffer register in even field (cgmse0) cgmse17 cgms data buffer register in even field (cgmse1) cgmse27 cgms data buffer register in even field (cgmse2) wss07 wss data buffer register (wss0) wss17 wss data buffer register (wss1) ccde1 6 cgmso06 cgmso26 cgmse06 cgmse16 cgmse26 wss06 wss16 ccde1 5 cgmso05 cgmso25 cgmse05 cgmse15 cgmse25 wss05 wss15 ccde1 4 cgmso04 cgmso24 cgmse04 cgmse14 cgmse24 wss04 wss14 ccde1 3 cgmso03 cgmso23 cgmse03 cgmse13 cgmse23 wss03 wss13 ccde1 2 cgmso02 cgmso22 cgmse02 cgmse12 cgmse22 wss02 wss12 ccde1 1 cgmso01 cgmso21 cgmse01 cgmse11 cgmse21 wss01 wss11 ccde1 0 cgmso00 cgmso20 cgmse00 cgmse10 cgmse20 wss00 wss10 25 26 27 28 29 2a 2b 2c 2d read read read read read read read read read write /read cgms data buffer register in odd field (cgms01) cgmso17 cgmso16 cgmso15 cgmso14 cgmso13 cgmso12 cgmso11 cgmso10 status7 stataus register (status) 20 read status6 status5 status4 status3 status2 status1 status0 vflag7 vbid flag register (vflag) 21 read vflag6 vflag5 vflag4 vflag3 vflag2 vflag1 vflag0 ccdo07 c. c. data buffer register in odd field (ccdo0) 22 read ccdo06 ccdo05 ccdo04 ccdo03 ccdo02 ccdo01 ccdo00 ccdo17 c. c. data buffer register in odd field (ccdo1) 23 read ccdo16 ccdo15 ccdo14 ccdo13 ccdo12 ccdo11 ccdo10 ccde07 c. c. data buffer register in even field (ccde0) 24 read ccde06 ccde05 ccde04 ccde03 ccde02 ccde01 ccde00 register list (continued) ? semiconductor msm7664 41/76 pedl7664-01 register parameters registers controlled from the i 2 c-bus are listed below. an asterisk (*) indicates that the register setting value is the default value. mode register a (mra) write only ? semiconductor msm7664 42/76 pedl7664-01 mrb[7:6] synchronization mode *00: fifo-1 (use internal memory) 01: fifo-2 (use internal memory) 10: fm-1 (use external memory, external control) 11: fm-2 (use external memory, control signals supplied from m[7:4]) note: in the fifo-1 mode, the number of pixels per 1h is output at the standard setting value. in the fifo-2 mode, the number of pixels per 1h is fixed in accordance with an input h period and output. in the fm-1 and fm-2 modes, a decoded result is output without any changes according to the sync signal. a field memory is required externally to output the fixed number of pixels in those modes. in the fm-2 mode, a field memory control signal is output from the pin m[7:4]. mrb[5] color killer mode *0: auto color killer (chrominance signal level is set to "0" if the color burst level is below the specified value.) *1: forced color killer (chrominance signal level is forced to "0".) mrb[4] blue back 0: off (video signal is demodulated and output regardless of synchronization detection.) *1: auto (blue back is output when synchro- nization is not detected.) mrb[3:2] clamp mode *00: analog clamp 01: analog, digital hybrid clamp 10: digital clamp (hsy clamp) 11: undefined clamp mode is selected. mrb[1:0] y/c separation mode *00: adaptive comb filter (correlation of 3 lines is monitored and operating mode is selected.) 01: non-adaptive comb filter (operating mode is always fixed.) 10: use trap filter. (comb filter is not used.) 11: undefined note: adaptive comb filter 2/3-line comb filter for ntsc comb filter/trap filter for pal non-adaptive comb filter 3-line comb filter for ntsc 2-line cosine comb filter for pal register name default recommended value mrb[7] mrb[6] mrb[5] mrb[4] mrb[3] mrb[2] mrb[1] mrb[0] 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 mode register b (mrb) write only ? semiconductor msm7664 43/76 pedl7664-01 hsyt[7:4] hsy start trimmer ( 8 pixels) $c to $b (*$0): C4 to +11 (C32 to +88 pixels) hsyt[3:0] hsy stop trimmer ( 8 pixels) $c to $b (*$0): C4 to +11 (C32 to +88 pixels) note: the hsyt signal provides the clamp timing to the a/d converter during digital clamp or hybrid clamp mode. because this signal can move to the pedestal position, the pedestal clamp can be used. however, this signal can not be observed from outside. register name default recommended value hsyt[7] hsyt[6] hsyt[5] hsyt[4] hsyt[3] hsyt[2] hsyt[1] hsyt[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mrc[7] ntsc/pal auto select 0: fix *1: auto note: this register decides automatically when the sampling frequency of input signals is itu-rbt.601. mrc[6] pixel alignment *0: use pixel position compensating circuit. 1: do not use pixel position compensating circuit. mrc[5] pixel sampling rate *0: (4:2:2) 1: (4:1:1) mrc[4] data-pass control *0: use decimator at 2x sampling. 1: do not use decimator. note: this register is valid when a 2x clock (27 mhz) is input. mrc[3] sav, eav v-status *0: during blanking, v = 1 1: during blanking, while vbi data is not detected, v = 1 mrc[2] rgb output level *0: 0 to 255 1: 16 to 235 mrc[1:0] undefined set to 0 horizontal sync trimmer (hsyt) write only ? semiconductor msm7664 44/76 pedl7664-01 hvalt[7:4] hvalid start trimmer ( 2 pixels) $8 to $7 (*$0): C8 to +7 (C16 to +14 pixels) hvalt[3:0] hvalid stop trimmer ( 2 pixels) $8 to $7 (*$0): C8 to +7 (C16 to +14 pixels) note: hvalid start position and end position are changed. register name default recommended value hvalt hvalt hvalt hvalt hvalt hvalt hvalt hvalt 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [7] [6] [5] [4] [3] [2] [1] [0] hsdl[7:0] hsync_l delay trimmer ( 1 pixel) $80 to $7f (*$00): C128 to +127 (C128 to +127 pixels) note: the hsync_l sync signal output position is adjusted. horizontal valid trimmer (hvalt) write only ? semiconductor msm7664 45/76 pedl7664-01 register name default recommended value vvalt vvalt vvalt vvalt vvalt vvalt vvalt vvalt 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [7] [6] [5] [4] [3] [2] [1] [0] vvalt[7:4] vvalid start trimmer ( 1 line) $8 to $7 (*$0): C8 to +7 vvalt[3:0] vvalid stop trimmer ( 1 line) $8 to $7 (*$0): C8 to +7 note: vvalid start position and end position are changed. luminance control (lumc) write only ? semiconductor msm7664 46/76 pedl7664-01 agclf[7:6] agc loop filter time constant 00: slow *01: medium 10: fast 11: mgc mode note: the agc convergence time is determined. these registers converge about 4 times faster by slow-medium-fast steps. in the mgc mode, the amplification is determined by reference level. set the ssepl[7] value to a 0 when the mgc mode is used. agclf[5:0] agc reference level $20 to $1f (*$00): C32 to +31 sync separation level (ssepl) write only ? semiconductor msm7664 47/76 pedl7664-01 chrc[7] color-killer mode *0: preset always the color killer to off at the top of field. 1: maintain the previous field status when the device is in an out-of-synchronization state at tha top of field. chrc[6:4] u, v-filter threshold setting of u/v averaging processing *000: do not do avaraging. 001: level difference 4 010: level difference 8 011: level difference 12 100: level difference 16 101: level difference 20 110: level difference 24 111: always do averaging. note: when in the output mode, u and v data can be averaged on the preceding and following lines. at that time, when the level difference is set, averaging operation is performed on each line taking the level as the threshold. chrc[3] c-output level limiter *0: off 1: on note: control range while limiter is on: 16 to 224 chrc[2] chroma bandpass filter 0: off *1: on chrc[1:0] color kill threshold factor 00: 0.500 color burst level *01: 0.250 color burst level 10: 0.125 color burst level 11: color killer off note: the color killer decision level is selected based upon color burst ratio. register name default recommended value chrc[7] chrc[6] chrc[5] chrc[4] chrc[3] chrc[2] chrc[1] chrc[0] 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 chrominance control (chrc) write only ? semiconductor msm7664 48/76 pedl7664-01 register name default recommended value opcy[7] opcy[6] opcy[5] opcy[4] opcy[3] opcy[2] opcy[1] opcy[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 hue control (hue) write only ? semiconductor msm7664 49/76 pedl7664-01 omr[7] hsync output timing select *0: hsync output signal is detected near sync threshold and sync tip. 1: hsync output signal is detected at sync threshold setting position. note: when the hsync output signal is detected at sync threshold setting position, it is hardly affected by noise. omr[6] vsync output timing select *0: vsync_l is synchronized to hsync_l and then output 1: vsync_l is output when a vsync input signal is detected. note: when a non-standard signal is decoded, the output is stabilized after the vsync_l input signal is detected (setting 1). omr[5:3] undefined set to 0 omr[2] hi-z output in sleep mode *0: active 1: hi-z note: this register selects either normal or hi-z as the output pin status in sleep mode. omr[1] status2 output mode *0: ntsc/pal identification 1: hlock sync detection omr[0] status3 output mode *0: tv/vcr identification 1: csync note: omr[1:0] correspond to the status[2:3] output of output pins. register name default recommended value omr[7] omr[6] omr[5] omr[4] omr[3] omr[2] omr[1] omr[0] 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 register name default recommended value opcc[7] opcc[6] opcc[5] opcc[4] opcc[3] opcc[2] opcc[1] opcc[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 output phase control for data c (opcc) write only ? semiconductor msm7664 50/76 pedl7664-01 adc1[7] video amp select *0: use 1: do not use adc1[6] undefined set to 0 adc1[5:4] clamp current select *00: 0.10 01: 0.05 10: 0.30 11: 0.80 adc1[3] undefined set to 0 adc1[2:0] adc input select *000: adi-vin1 (composite-1) 001: adi-vin2 (composite-2) 010: adi-vin3 (composite-3) 011: adi-vin4 (composite-4) 100: adi-vin5 (composite-5) 101: adi-vin1 (y-1), ad2-vin5 (c-1) 110: adi-vin2 (y-1), ad2-vin6 (c-1) 111: prohibited setting (adc enters sleep state) note: when the lsi is used in composite video mode, input clocks or do resetting after setting s-video mode (101), (110) before setting composite video mode. adc register 2 (adc2) write only ? semiconductor msm7664 51/76 pedl7664-01 zld[7:3] undefined set to 0 zld[2:0] 0 level detect width ( 8 pixels) 000: undefined 001: 8 pixels *010: 16 pixels 011: 24 pixels 100: 32 pixels 101: 40 pixels 110: 48 pixels 111: 56 pixels note: these registers decide the continuance of sync tip level and its result is reflected in agc gain. the stability can be obtained from higher values. register name default recommended value zld[7] zld[6] zld[5] zld[4] zld[3] zld[2] zld[1] zld[0] 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 adc3[7] undefined set to 0 adc3[6:4] adc gain control margin level select 000: 10 mv 001: 20 mv *010: 40 mv 011: 80 mv 100: 160 mv 101, 110, 111: undefined adc3[3] undefined set to 0 adc3[2:0] adc gain control line select 000: 1 line 001: 2 lines *010: 4 lines 011: 8 lines 100: 16 lines 101, 110, 111: undefined note: these registers determine the analog gain control decision level. the stability can be obtained from higher values. 0 level detect register (zld) write only ? semiconductor msm7664 52/76 pedl7664-01 y/c separation circuit option register (ycsc) write only ? semiconductor msm7664 53/76 pedl7664-01 closed caption detected-1 register (ccd1) write only ? semiconductor msm7664 54/76 pedl7664-01 agc pulse detected-1 register (agcd1) write only ? semiconductor msm7664 55/76 pedl7664-01 misc[7:2] undefined set to 0 misc[1:0] tri-state control of output pin *00: output enable 01: all data outputs are hi-z. 10: all output pins are hi-z. 11: undefined reset data request for vbid function register (aireg) write only ? semiconductor msm7664 56/76 pedl7664-01 status register (status) read only ? semiconductor msm7664 57/76 pedl7664-01 ccdo0[7:0] bits 7 to 0 of c.c. data in odd field c.c. data buffer register in odd field (ccdo1) read only ? semiconductor msm7664 58/76 pedl7664-01 cgmso0[7:0]bits 7 to 0 of cgms data in odd field cgms data buffer register in odd field (cgmso1) read only ? semiconductor msm7664 59/76 pedl7664-01 cgms data buffer register in even field (cgmse0) read only ? semiconductor msm7664 60/76 pedl7664-01 register name default recommended value wss1[7] wss1[6] wss1[5] wss1[4] wss1[3] wss1[2] wss1[1] wss1[0] register name default recommended value wss0[7] wss0[6] wss0[5] wss0[4] wss0[3] wss0[2] wss0[1] wss0[0] wss0[7:0] bits 7 to 0 of wss data wss data buffer register (wss1) read only ? semiconductor msm7664 61/76 pedl7664-01 output pin control table *1) mra[7:6] are valid when in internal register mode. *2) y[7:0], c[7:0], b[7:0], m[7:3], hsync_l, vsync_l, hvalid, vvalid, status[3:1] pins other than the pins defined as hi-z pin are active. output mode itu-rbt.656 itu-rbt.656 itu-rbt.656 itu-rbt.656 itu-rbt.656 itu-rbt.656 mode[3:2] or mra[7:6] *1 00 00 00 00 00 00 sleep 0 (normal operation) 0 (normal operation) 0 (normal operation) 0 (normal operation) 1 (sleep) 1 (sleep) omr[2] 0 or 1 0 or 1 0 or 1 0 or 1 0 0 misc[1:0] 00 01 10 11 00 01 hi-z pin c[7:0], b[7:0] y[7:0], c[7:0], b[7:0], m[7:3] *2 undefined c[7:0], b[7:0] c[7:0], b[7:0] itu-rbt.656 itu-rbt.656 itu-rbt.656 8-bit ycbcr 8-bit ycbcr 8-bit ycbcr 8-bit ycbcr 8-bit ycbcr 8-bit ycbcr 8-bit ycbcr 8-bit ycbcr 8-bit ycbcr 16-bit ycbcr 16-bit ycbcr 16-bit ycbcr 16-bit ycbcr 16-bit ycbcr 16-bit ycbcr 16-bit ycbcr 16-bit ycbcr 16-bit ycbcr 24-bit rgb 24-bit rgb 24-bit rgb 24-bit rgb 24-bit rgb 24-bit rgb 24-bit rgb 24-bit rgb 24-bit rgb 00 00 00 01 01 01 01 01 01 01 01 01 10 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 11 1 (sleep) 1 (sleep) 1 (sleep) 0 (normal operation) 0 (normal operation) 0 (normal operation) 0 (normal operation) 1 (sleep) 1 (sleep) 1 (sleep) 1 (sleep) 1 (sleep) 0 (normal operation) 0 (normal operation) 0 (normal operation) 0 (normal operation) 1 (sleep) 1 (sleep) 1 (sleep) 1 (sleep) 1 (sleep) 0 (normal operation) 0 (normal operation) 0 (normal operation) 0 (normal operation) 1 (sleep) 1 (sleep) 1 (sleep) 1 (sleep) 1 (sleep) 0 0 1 0 or 1 0 or 1 0 or 1 0 or 1 0 0 0 0 1 0 or 1 0 or 1 0 or 1 0 or 1 0 0 0 0 1 0 or 1 0 or 1 0 or 1 0 or 1 0 0 0 0 1 10 11 all 00 01 10 11 00 01 10 11 all 00 01 10 11 00 01 10 11 all 00 01 10 11 00 01 10 11 all c[7:0], b[7:0] c[7:0], b[7:0] *2 c[7:0], b[7:0] y[7:0], c[7:0], b[7:0], m[7:3] *2 undefined c[7:0], b[7:0] c[7:0], b[7:0] c[7:0], b[7:0] c[7:0], b[7:0] *2 c[7:0], b[7:0] y[7:0], c[7:0], b[7:0], m[7:3] *2 undefined b[7:0] b[7:0] b[7:0] b[7:0] *2 none y[7:0], c[7:0], b[7:0], m[7:3] *2 undefined none none none none *2 ? semiconductor msm7664 62/76 pedl7664-01 relationship between register setting value and adjusted value horizontal sync trimmer position adjustment of sync tip clamp timing signal hsyt [7:4] :adjusting the starting position register setting value (0x) adjusted value (pixel) cdef0*123456789ab C32 C24 C16 C8 0 +8 +16 +24 +32 +40 +48 +56 +64 +72 +80 +88 hsyt [3:0] :adjusting the end position cdef0*123456789ab C32 C24 C16 C8 0 +8 +16 +24 +32 +40 +48 +56 +64 +72 +80 +88 register setting value (0x) adjusted value (pixel) horizontal sync delay adjustment of the starting position of horizontal sync signal hsdl [7:0] unit: [pixel] 89abcdef0*1234567 msb[7 : 4] C128 C112 C96 C80 C64 C48 0 +16 +32 +48 +64 +80 +96 +112 C127 C111 C95 C79 C63 C47 +1 C126 C110 C94 C78 C62 C46 +2 C125 C109 C93 C77 C61 C45 +3 C124 C108 C92 C76 C60 C44 +4 C123 C107 C91 C75 C59 C43 +5 C122 C106 C90 C74 C58 C42 +6 C121 C105 C89 C73 C57 C41 +7 C120 C104 C88 C72 C56 C40 +8 C119 C103 C87 C71 C55 C39 +9 C118 C102 C86 C70 C54 C38 +10 C117 C101 C85 C69 C53 C37 +11 C116 C100 C84 C68 C52 C36 +12 C115 C99 C83 C67 C51 C35 +13 C114 C98 C82 C66 C50 C34 +14 C113 C97 C81 C65 C49 C33 +15 0* 1 2 3 4 5 6 7 8 9 a b c d e f lsb [3 : 0] C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 +17 +18 +19 +20 +21 +22 +23 +24 +25 +26 +27 +28 +29 +30 +31 +33 +34 +35 +36 +37 +38 +39 +40 +41 +42 +43 +44 +45 +46 +47 +49 +50 +51 +52 +53 +54 +55 +56 +57 +58 +59 +60 +61 +62 +63 +65 +66 +67 +68 +69 +70 +71 +72 +73 +74 +75 +76 +77 +78 +79 +81 +82 +83 +84 +85 +86 +87 +88 +89 +90 +91 +92 +93 +94 +95 +97 +98 +99 +100 +101 +102 +103 +104 +105 +106 +107 +108 +109 +110 +111 +113 +114 +115 +116 +117 +118 +119 +120 +121 +122 +123 +124 +125 +126 +127 register setting value (0x) ? semiconductor msm7664 63/76 pedl7664-01 horizontal valid trimmer position adjustment of horizontal valid pixel timing signal hvalt [7:4] :adjusting the starting position 89abcdef0*1234567 C16 C14 C12 C10 C8 C6 C4 C2 0 +2 +4 +6 +8 +10 +12 +14 register setting value (0x) adjusted value (pixel) hvalt [3:0] :adjusting the end position 89abcdef0*1234567 C16 C14 C12 C10 C8 C6 C4 C2 0 +2 +4 +6 +8 +10 +12 +14 register setting value (0x) adjusted value (pixel) vertical valid trimmer position adjustment of vertical valid line timing signal vvalt [7:4] :adjusting the starting position vvalt [3:0] :adjusting the end position 89abcdef0*1234567 C8 C7 C6 C5 C4 C3 C2 C1 0 +1 +2 +3 +4 +5 +6 +7 register setting value (0x) adjusted value (line) 89abcdef0*1234567 C8 C7 C6 C5 C4 C3 C2 C1 0 +1 +2 +3 +4 +5 +6 +7 register setting value (0x) adjusted value (line) agc loop filter control agclf [5:0] :adjusting agc sync level unit: [ire], default: 40ire 2 3 0* 1 msb [5 : 4] 0 +16 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15 1 2 3 4 5 6 7 8 9 a b c d e f lsb [3 : 0] C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 +17 +18 +19 +20 +21 +22 +23 +24 +25 +26 +27 +28 +29 +30 +31 0* 1 2 3 4 5 6 7 8 9 a b c d e f lsb register setting value (0x) ? semiconductor msm7664 64/76 pedl7664-01 sync separation level ssepl [6:0] :adjusting the blanking level unit: [ire], default: 40ire 45670*123 msb [6 : 4] C64 C48 0 +16 +32 +48 C63 C47 +1 C62 C46 +2 C61 C45 +3 C60 C44 +4 C59 C43 +5 C58 C42 +6 C57 C41 +7 C56 C40 +8 C55 C39 +9 C54 C38 +10 C53 C37 +11 C52 C36 +12 C51 C35 +13 C50 C34 +14 C49 C33 +15 0* 1 2 3 4 5 6 7 8 9 a b c d e f [3 : 0] C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 +17 +18 +19 +20 +21 +22 +23 +24 +25 +26 +27 +28 +29 +30 +31 +33 +34 +35 +36 +37 +38 +39 +40 +41 +42 +43 +44 +45 +46 +47 +49 +50 +51 +52 +53 +54 +55 +56 +57 +58 +59 +60 +61 +62 +63 lsb lsb register setting value (0x) ? semiconductor msm7664 65/76 pedl7664-01 acc loop filter control acclf [4:0] :adjusting the color burst level unit: [ire], default: 40ire 10* msb [4] 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15 1 2 3 4 5 6 7 8 9 a b c d e f lsb [3 : 0] C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 0* 1 2 3 4 5 6 7 8 9 a b c d e f lsb register setting value (0x) ? semiconductor msm7664 66/76 pedl7664-01 hue control adjustment of color subcarrier phase hue [7:0] unit: [degree] 89abcdef0*1234567 msb [7 : 4] C180.0 C157.5 C135.0 C112.5 C90.0 C67.5 +0.0 +22.5 +45.0 +67.5 +90.0 +112.5 +135.0 +157.5 C178.6 C156.1 C133.6 C111.1 C88.6 C66.1 +1.4 C177.2 C154.7 C132.2 C109.7 C87.2 C64.7 +2.8 C175.8 C153.3 C130.8 C108.3 C85.8 C63.3 +4.2 C174.4 C151.9 C129.4 C106.9 C84.4 C61.9 +5.6 C173.0 C150.5 C128.0 C105.5 C83.0 C60.5 +7.0 C171.6 C149.1 C126.6 C104.1 C81.6 C59.1 +8.4 C170.2 C147.7 C125.2 C102.7 C80.2 C57.7 +9.8 C168.8 C146.3 C123.8 C101.3 C78.8 C56.3 +11.3 C167.3 C144.8 C122.3 C99.8 C77.3 C54.8 +12.7 C165.9 C143.4 C120.9 C98.4 C75.9 C53.4 +14.1 C164.5 C142.0 C119.5 C97.0 C74.5 C52.0 +15.5 C163.1 C140.6 C118.1 C95.6 C73.1 C50.6 +16.9 C161.7 C139.2 C116.7 C94.2 C71.7 C49.2 +18.3 C160.3 C137.8 C115.3 C92.8 C70.3 C47.8 +19.7 C158.9 C136.4 C113.9 C91.4 C68.9 C46.4 +21.1 0* 1 2 3 4 5 6 7 8 9 a b c d e f lsb [3 : 0] C45.0 C43.6 C42.2 C40.8 C39.4 C38.0 C36.6 C35.2 C33.8 C32.3 C30.9 C29.5 C28.1 C26.7 C25.3 C23.9 C22.5 C21.1 C19.7 C18.3 C16.9 C15.5 C14.1 C12.7 C11.3 C9.8 C8.4 C7.0 C5.6 C4.2 C2.8 C1.4 +23.9 +25.3 +26.7 +28.1 +29.5 +30.9 +32.3 +33.8 +35.2 +36.6 +38.0 +39.4 +40.8 +42.2 +43.6 +46.4 +47.8 +49.2 +50.6 +52.0 +53.4 +54.8 +56.3 +57.7 +59.1 +60.5 +61.9 +63.3 +64.7 +66.1 +68.9 +70.3 +71.7 +73.1 +74.5 +75.9 +77.3 +78.8 +80.2 +81.6 +83.0 +84.4 +85.8 +87.2 +88.6 +91.4 +92.8 +94.2 +95.6 +97.0 +98.4 +99.8 +101.3 +102.7 +104.1 +105.5 +106.9 +108.3 +109.7 +111.1 +113.9 +115.3 +116.7 +118.1 +119.5 +120.9 +122.3 +123.8 +125.2 +126.6 +128.0 +129.4 +130.8 +132.2 +133.6 +136.4 +137.8 +139.2 +140.6 +142.0 +143.4 +144.8 +146.3 +147.7 +149.1 +150.5 +151.9 +153.3 +154.7 +156.1 +158.9 +160.3 +161.7 +163.1 +164.5 +165.9 +167.3 +168.8 +170.2 +171.6 +173.0 +174.4 +175.8 +177.2 +178.6 register setting value (0x) ? semiconductor msm7664 67/76 pedl7664-01 sync. threshold level adjust adjustment of the detection threshold of horizontal sync signal shtr [7:0] unit: [ire]/2 01*23456789abcdef msb [7 : 4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 0 1 2 3 4 5 6 7 8 9 a b c d e* f lsb [3 : 0] 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 register setting value (0x) ? semiconductor msm7664 68/76 pedl7664-01 filter characteristics 0 C20 C40 C60 C80 C100 0123 fre q uenc y [ mhz ] band pass filter (ntsc itu-rbt.601) level [db] 456 0 C20 C40 C60 C80 C100 0123 fre q uenc y [ mhz ] band pass filter (pal itu-rbt.601) level [db] 456 ? semiconductor msm7664 69/76 pedl7664-01 0 C20 C40 C60 C80 C100 0123 fre q uenc y [ mhz ] trap filter (ntsc itu-rbt.601) level [db] 456 0 C20 C40 C60 C80 C100 0123 fre q uenc y [ mhz ] trap filter (pal itu-rbt.601) level [db] 456 ? semiconductor msm7664 70/76 pedl7664-01 0 C20 C40 C60 C80 C100 0123 frequency [mhz] prefilter level [db] 456 0 C20 C40 C60 C80 C100 0123 frequency [mhz] sharp filter level [db] 456 ? semiconductor msm7664 71/76 pedl7664-01 0 C20 C40 C60 C80 C100 0246 frequency [mhz] level [db] 81012 decimation filter ? semiconductor msm7664 72/76 pedl7664-01 basic application circuit examples 1) application circuit for fifo-1 and fifo-2 modes 4 msm7664 video lsi osc i 2 c controller 1 m f 2 1 m f video in (c input) sda scl reset_l av dd dav dd dv dd y(7:0) c(7:0) b(7:0) hvalid vvalid odd hsync_l vsync_l clkx2o clkxo clkx2 mode[3:0] dgnd dagnd agnd 10 m f 10 m f 1 m f 10 m f 10 m f 1 m f 10 k w video in (composite y input) 4.7 k w 4.7 k w 3.3 v or 5 v 1000 pf 47 m f 1000 pf 47 m f 1000 pf 47 m f vin(1:4) vrt1 ampout adin1 clpout1 vrcl1 vrb1 vin(5:6) vrt2 ampout2 adin2 clpout2 vrb2 75 w 75 w 75 w lpf lpf 75 w 100 w ampout lpf adin 250 pf ? connect the m7664 decoder and a video lsi device according to the output interface (itu- rbt.656, 8-bit [ycbcr], 16-bit [ycbcr], rgb). ? video input can be four composite inputs or two s-video inputs. ? connect unused video input pins to agnd. if a composite signal is input, the c input side (video amp, a/d converter, etc.) will be in the off operation state. ? if the input is limited to the composite signal, connect vin (5:6), vrt2, vrb2, ampout2, adin2, and clpout2 pins to agnd. externally attached components such as capacitors may be removed. ? set the mode[3:0] pins to the prescribed setting. ? supply power and gnd for analog, a/d, and digital circuits on the circuit board should be separated at the power source wherever possible. power and gnd lines for analog and a/d circuits must be wide and low impedance. ? semiconductor msm7664 73/76 pedl7664-01 2) application circuit for fm-1 and fm-2 modes ? select either 16-bit [ycbcr] or rgb output as the output interface. ? number of field memories utilized 16-bit [ycbcr]: use 2 field memories. rgb: use 3 field memories. ? video input can be four composite inputs or two s-video inputs. ? connect unused video input pins to agnd. if a composite signal is input, the c input side (video amp, a/d converter, etc.) will be in the off operation state. ? if the input is limited to the composite signal, connect vin (5:6), vrt2, vrb2, ampout2, adin2, and clpout2 pins to agnd. externally attached components such as capacitors may be removed. ? set the mode[3:0] pins to the prescribed setting. ? for the fm-1 mode setting, externally generate and supply control signals for the field memory. ? for the fm-2 mode setting, memory control signals from m[7:4] can be supplied to the field memory. ? for the fm-2 mode setting, the output timing for hsync_l, vsync_l, odd, vvalid, and hvalid becomes the memory read timing. data output from memory is aligned with the various sync signal timings. (see page 31 and page 32) ? supply power and gnd for analog, a/d, and digital circuits on the circuit board should be separated at the power source wherever possible. power and gnd lines for analog and a/d circuits must be wide and low impedance. msm7664 video lsi osc i 2 c controller video in (c input) sda scl reset_l av dd dav dd dv dd y(7:0) c(7:0) b(7:0) hvalid vvalid odd hsync_l vsync_l clkx2o clkx2 mode[3:0] dgnd dagnd agnd 10 m f 10 m f 1 m f 10 m f 1 m f 10 k w video in (composite y input) 4.7 k w 4.7 k w 3.3 v or 5 v 1000 pf 47 m f 1000 pf 47 m f 1000 pf 47 m f vin(1:4) vrt1 ampout adin1 clpout1 vrcl1 vrb1 vin(5:6) vrt2 ampout2 adin2 clpout2 vrb2 memory control signal m[7:4] field mem- ory field mem- ory clkxo 75 w 75 w 4 1 m f 2 1 m f 10 m f 75 w lpf 75 w 100 w ampout lpf adin 250 pf lpf ? semiconductor msm7664 74/76 pedl7664-01 notes on use ? the decoder and encoder ics have multiple registers for improving and stabilizing their characteristics, and these registers have a function to set the default values for standard signals. video signals different from standard signals can be input depending on user applications. in this case, it is recommended to set each register to different values from the default values to stabilize the decode operations under the user's requirements. please contact us for these register settings. ? stable decode operations cannot always be guaranteed depending on input video signals. each register can vary its setting values over a wide range but stable operations cannot be guaranteed for all setting values. ? semiconductor msm7664 75/76 pedl7664-01 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, tqfp, lqfp, soj, qfj (plcc), shp, and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). tqfp100-p-1414-0.50-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.55 typ. mirror finish ? semiconductor msm7664 76/76 pedl7664-01 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 1999 oki electric industry co., ltd. printed in japan |
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